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d a t a sh eet objective speci?cation 2003 feb 25 integrated circuits pcf8890 240 + 1 outputs tft lcd gate driver
2003 feb 25 2 philips semiconductors objective speci?cation 240 + 1 outputs tft lcd gate driver pcf8890 contents 1 features 2 application 3 general description 4 ordering information 5 block diagram 6 pinning 7 functional description 7.1 power-up sequence 7.2 shift register 7.3 i/o signal voltage levels 7.4 pulse micro timing 7.5 waveforms 8 programming 9 limiting values 10 handling 11 dc characteristics 12 ac characteristics 13 application information 14 open short diagrams 15 bonding pad information 16 tray information 17 data sheet status 18 definitions 19 disclaimers
2003 feb 25 3 philips semiconductors objective speci?cation 240 + 1 outputs tft lcd gate driver pcf8890 1 features low power tft lcd gate driver and dc/dc controller 240 + 1 outputs programmable number of active outputs from 1 to 240 + 1 4-level gate driving, 4-level hapd (philips) driving scheme (1 high and 3 low levels) and additional v ss step for power reduction on-chip dc/dc controller high output voltage range: v vh = +20 v (maximum programmed indirectly via v1 settings) and v ee = - 20 v (minimum) row inversion with pre-pulse operating frequency: up to 100 khz automatic reset for shift register by frame start supports line and frame inversion for gate coupled driving low power consumption optimized for battery operation slim chip layout for cog, tcp and cof applications compatible with pcf8880 source driver. 2 application the chip set pcf8890 and pcf8880 is optimized for low power colour tft lcds in portable applications such as cellular phones, pdas and mp3 players, instrumentation, automotive informations system, etc. the gate driver can be used for small to medium sized panels with up to 240 lines (e.g. 1/4 vga) and maximal 300 pf load per line. 3 general description pcf8890 is a high-voltage cmos ic designed to drive 240 + 1 gate lines of a tft lcd with an output voltage up to 40 v. the device includes: a 241-bit shift register with high-voltage output stages a switch matrix with 5 output levels (for 4-level driving scheme plus v ss ) an automatic reset by pin framestart a dc/dc controller and regulator a voltage generator for all output levels of the gate driver and for the companion source driver (pcf8880). the device is manufactured in a high-voltage n-well cmos technology. the pcf8890 is completely controlled by the pcf8880. no interface to external controller systems is required. the gate driver is tailored to panels which operate with a patented gate coupled driving. on the panel, the storage capacitor must be connected to the next row. thus, an extra row line is required to invert the last line of the display. 4 ordering information type number package name description version PCF8890U - chip assembly on the glass module - - chip assembly on foil (tbf) -
2003 feb 25 4 philips semiconductors objective speci?cation 240 + 1 outputs tft lcd gate driver pcf8890 5 block diagram fig.1 block diagram. (1) dummy = 1, 243, 247 to 325, 345, 346, 350, 351, 380 and 381. (2) v ee = 246, 327 to 329 and 382. (3) v bat = 244, 342 to 344 and 384. (4) v dd(host) = 356 to 358. (5) v ss = 245, 326, 334, 341, 348, 352 to 355, 379 and 383. a ndbook, full pagewidth mdb111 shift register switch matrix voltage generator and control framestart sysrst_n vbg vbgref iref vctrl0 vctrl1 v dda(comp) dcdcclk r1 to r240 r241 v1 v2 v3 v4 vok tp0 v ss v bat v ee dummy v dd(host) tp1 tp2 tp3 tp4 tp5 tp6 swctrl0 swctrl1 vh pcf8890 rowclk0 rowclk1 rowinv 366 2) 1) 3) 4) 5) 367 368 369 360 337, 338 335, 336 332, 333 330, 331 359 347 349 242 2 to 241 361 362 363 364 365 370 371 375 376 377 378 373 374 372 339, 340 240
2003 feb 25 5 philips semiconductors objective speci?cation 240 + 1 outputs tft lcd gate driver pcf8890 6 pinning symbol pad type (1) description dummy 1, 243, 247 to 325, 345, 346, 350, 351, 380, 381 - r1 to r240 2 to 241 o row output 1 to 240; 4-level high-voltage output to the tft gate and storage capacitor; not connected if display with less than 240 lines is used r241 242 o row output 241; 3-level high-voltage pre-pulse output to the storage capacitor; not connected if display with less than 241 lines is used v bat 244, 342 to 344, 384 s battery supply voltage; input for dc/dc converter and power supply; connect to battery v ss 245, 326, 334, 341, 348, 352 to 355, 379, 383 s logic ground v ee 246, 327 to 329, 382 s chip bulk; generated chip bulk voltage (used for external capacitor) v4 330 to 331 s gate low pre-pulse level output; not used and not connected (only used for testing) v3 332 to 333 s gate low-level voltage output; not used and not connected (only used for testing) v2 335 to 336 s gate high pre-pulse level output; not used and not connected (only used for testing) v1 337 to 338 s regulated high-level voltage output; (used for external capacitor) vh 339 to 340 s generated high-level voltage; (used for external capacitor) swctrl0 347 o switching control 0 output; controls the external switches of the dc/dc converter swctrl1 349 o switching control 1 output; controls the external switches of the dc/dc converter v dd(host) 356 to 358 s logic power supply voltage; power supply for digital circuitry vok 359 o generated voltages status output; used for start up of voltage generator; connect to vok input of pcf8880 sysrst_n 360 i system reset input; if sysrst_n = low the shift register is cleared and all analog blocks are switched off (no high-voltage available); connect to sysrst_n output of pcf8880 vbg 361 i band gap voltage input (1.22 v); connect to vbg output of pcf8880 vbgref 362 i band gap reference voltage input; high-ohmic reference voltage for band gap (0 v); connect to vbgref output of pcf8880 iref 363 i 2.2 m a current source for analog blocks input; connect to iref output of pcf8880 vctrl0 364 i voltage control 0 input; serial data link from the source driver for programming of the output levels; connect to vctrl0 output of pcf8880
2003 feb 25 6 philips semiconductors objective speci?cation 240 + 1 outputs tft lcd gate driver pcf8890 note 1. s = supply, o = output and i = input vctrl1 365 i voltage control 1 input; serial data link from the source driver for programming of the output levels; connect to vctrl1 output of pcf8880 framestart 366 i shift register for gate signals input; connect to framestart output of pcf8880 rowclk0 367 i shift register clock 0 input; the shift register data is shifted on the rising edge of rowclk0; connect to rowclk0 output of pcf8880 rowclk1 368 i shift register clock 1 input; connect to rowclk1 output of pcf8880 rowinv 369 i pre-pulse polarity control input; if rowinv = high, the pre-pulse is positive (v2), if rowinv = low, the pre-pulse is negative (v4); connect to rowinv output of pcf8880 v dda(comp) 370 i v dda comparator input; this signal is used for voltage generation; connect to v dda(comp) output of pcf8880 dcdcclk 371 i dc/dc converter chopping clock input; connect to dcdcclk output of pcf8880 tp6 372 i test pin 6: connect to v ss (used for testing) tp5 373 i test pin 5: connect to v ss (used for testing) tp4 374 i test pin 4: connect to v ss (used for testing) tp3 375 i test pin 3: connect to v ss (used for testing) tp2 376 i test pin 2: connect to v ss (used for testing) tp1 377 i test pin 1: connect to v ss (used for testing) tp0 378 i test pin 0: connect to v ss (used for testing) symbol pad type (1) description
2003 feb 25 7 philips semiconductors objective speci?cation 240 + 1 outputs tft lcd gate driver pcf8890 7 functional description 7.1 power-up sequence when powering up the device, a certain sequence of switching-on of the different supply voltages has to be followed (tbf). 7.2 shift register the shift register is controlled by the shift clock rowclk0. on the rising edge of rowclk0, the data is shifted from r1 to r241. 7.3 i/o signal voltage levels handbook, full pagewidth mdb112 vh v1 v dd(host) v ss logic inputs r1 to r240 v2 v3 v4 v ee fig.2 i/o signal voltage levels. 7.4 pulse micro timing handbook, full pagewidth mdb113 r(n - 1) r(n) rowclk0 rowclk1 r(n + 1) rowclk0 rowclk1 dcdcclk fig.3 pulse micro timing.
2003 feb 25 8 philips semiconductors objective speci?cation 240 + 1 outputs tft lcd gate driver pcf8890 7.5 waveforms handbook, full pagewidth mdb114 rowclk0 rowinv framestart r1 r2 r239 r240 r241 1 2 3 4 5 238 239 240 241 242 fig.4 shift operation.
2003 feb 25 9 philips semiconductors objective speci?cation 240 + 1 outputs tft lcd gate driver pcf8890 8 programming table 1 row driver voltage programming; v1 max limited by v ee and v bat (v1 = v bat +v ee ); v4 steps are the same as v3 step. v3 prog v3 (v) v1 (v) v2 (v) v4 (v) v ee (v) min. max. step min. max. step min. max. 11111 - 8.057 11.25 18.750 0.5 - 2.510 - 6.494 - 0.032 13.604 - 17.588 - 19.142 11110 - 8.057 11.25 18.750 0.5 - 2.510 - 6.494 - 0.031 13.604 - 17.588 - 19.142 11101 - 7.910 11.25 18.750 0.5 - 2.464 - 6.375 - 0.031 13.356 - 17.268 - 18.793 11100 - 7.769 11.25 18.750 0.5 - 2.420 - 6.261 - 0.030 13.118 - 16.959 - 18.457 11011 - 7.633 11.25 18.750 0.5 - 2.377 - 6.151 - 0.030 12.887 - 16.661 - 18.133 11010 - 7.501 11.25 18.750 0.5 - 2.336 - 6.045 - 0.029 12.665 - 16.374 - 17.820 11001 - 7.374 11.25 18.750 0.5 - 2.297 - 5.943 - 0.029 12.450 - 16.096 - 17.518 11000 - 7.251 11.25 18.750 0.5 - 2.258 - 5.844 - 0.028 12.242 - 15.827 - 17.225 10111 - 7.132 11.25 18.750 0.5 - 2.221 - 5.748 - 0.028 12.041 - 15.568 - 16.943 10110 - 7.016 11.25 18.750 0.5 - 2.185 - 5.655 - 0.027 11.847 - 15.316 - 16.669 10101 - 6.905 11.25 18.750 0.5 - 2.151 - 5.565 - 0.027 11.659 - 15.073 - 16.404 10100 - 6.797 11.25 18.750 0.5 - 2.117 - 5.478 - 0.026 11.476 - 14.837 - 16.148 10011 - 6.692 11.25 18.599 0.5 - 2.084 - 5.394 - 0.026 11.300 - 14.609 - 15.899 10010 - 6.591 11.25 18.358 0.5 - 2.053 - 5.312 - 0.026 11.128 - 14.387 - 15.658 10001 - 6.492 11.25 18.124 0.5 - 2.022 - 5.232 - 0.025 10.962 - 14.172 - 15.424 10000 - 6.397 11.25 17.897 0.5 - 1.992 - 5.155 - 0.025 10.801 - 13.964 - 15.197 01111 - 6.304 11.25 17.676 0.5 - 1.964 - 5.081 - 0.025 10.644 - 13.761 - 14.976 01110 - 6.214 11.25 17.462 0.5 - 1.935 - 5.008 - 0.024 10.492 - 13.564 - 14.762 01101 - 6.126 11.25 17.254 0.5 - 1.908 - 4.937 - 0.024 10.344 - 13.373 - 14.554 01100 - 6.041 11.25 17.052 0.5 - 1.882 - 4.869 - 0.024 10.200 - 13.187 - 14.352 01011 - 5.958 11.25 16.855 0.5 - 1.856 - 4.802 - 0.023 10.060 - 13.006 - 14.155 01010 - 5.878 11.25 16.664 0.5 - 1.831 - 4.737 - 0.023 9.924 - 12.830 - 13.964 01001 - 5.799 11.25 16.477 0.5 - 1.806 - 4.674 - 0.023 9.792 - 12.659 - 13.777 01000 - 5.723 11.25 16.296 0.5 - 1.783 - 4.612 - 0.022 9.663 - 12.492 - 13.596 00111 - 5.648 11.25 16.119 0.5 - 1.759 - 4.552 - 0.022 9.537 - 12.330 - 13.419 00110 - 5.576 11.25 15.947 0.5 - 1.737 - 4.494 - 0.022 9.415 - 12.172 - 13.247 00101 - 5.505 11.25 15.779 0.5 - 1.715 - 4.437 - 0.021 9.295 - 12.018 - 13.079 00100 - 5.436 11.25 15.616 0.5 - 1.693 - 4.381 - 0.021 9.179 - 11.867 - 12.916 00011 - 5.369 11.25 15.456 0.5 - 1.672 - 4.327 - 0.021 9.066 - 11.721 - 12.756 00010 - 5.304 11.25 15.300 0.5 - 1.652 - 4.274 - 0.021 8.955 - 11.578 - 12.600 00001 - 5.240 11.25 15.148 0.5 - 1.632 - 4.223 - 0.020 8.847 - 11.438 - 12.448 00000 - 5.177 11.25 15.000 0.5 - 1.613 - 4.173 - 0.020 8.742 - 11.302 - 12.300
2003 feb 25 10 philips semiconductors objective speci?cation 240 + 1 outputs tft lcd gate driver pcf8890 9 limiting values in accordance with the absolute maximum rating system (iec 60134); see notes 1 and 2; all values with respect to v ss =0v. notes 1. stresses above those listed under limiting values may cause permanent damage to the device. 2. parameters are valid over operating temperature range unless otherwise specified. all voltages are with respect to v ss unless otherwise noted. 3. the storage temperature specifies the temperature range within which the chip will not be damaged when it is not powered. 10 handling inputs and outputs are protected against electrostatic discharge in normal handling. however, to be totally safe, it is recommended to take standard precautions appropriate for handling mos devices (see handling mos devices ). symbol parameter condition min. max. unit v bat battery supply voltage v ss - 0.3 v ss + 7.0 v v ss interface ground voltage v ee - 0.3 v ee +10 v v dd(host) interface high-voltage supply voltage v ss - 0.3 v ss + 7.0 v v ee bulk voltage v vh - 45 v vh + 0.3 v v vh not regulated high-voltage v ee - 0.3 v ee +45 v v vbgref band gap reference voltage v ss - 0.3 v dd(host) + 0.3 v v v1 drive 1 voltage v ee - 0.3 v ee +45 v v v2 drive 2 voltage v ee - 0.3 v ee +45 v v v3 drive 3 voltage v ee - 0.3 v ee +45 v v v4 drive 4 voltage v ee - 0.3 v ee +45 v v i voltage on all digital input pins v ss - 0.3 v dd(host) + 0.3 v v o voltage on all digital output pins v ss - 0.3 v dd(host) + 0.3 v v swctrl voltage on all switch control pins v ss - 0.3 v bat + 0.3 v v r(x) voltage on all row pins v ss - 0.3 v bat + 0.3 v t oper operating temperature - 40 +85 c t stg storage temperature note 3 - 55 +125 c
2003 feb 25 11 philips semiconductors objective speci?cation 240 + 1 outputs tft lcd gate driver pcf8890 11 dc characteristics v dd(host) = 1.8 v; v bat = 2.7 to 4.5 v; v ss =0v; t amb = - 40 to +85 c; unless otherwise speci?ed. symbol parameter conditions min. typ. max. unit supplies v bat battery supply voltage 2.7 - 4.5 v v dd(host) interface high-voltage supply voltage 1.8 - 3.6 v v vh not regulated high-voltage v bat - v ee tbf v bat + 18 tbf v v ee bulk voltage tbf - 18.5 tbf v i bat battery supply current v dd(host) = 2.7 v; f osc = 625 khz; v v1 =15v; v v2 = - 4v; v v2 = - 12 v; v ee =20v -- tbf m a i bat(idle) idle battery supply current v dd(host) = 2.7 v; f osc =0; v v1 =v v2 =v v4 =0 v ee =0 -- tbf m a i dd(host) interface high-voltage supply current v dd(host) = 2.7 v; f osc = 625 khz -- tbf m a i dd(idle) idle interface high-voltage supply current v dd(host) = 2.7 v; f osc =0; -- tbf m a driver outputs; pins v1, v2, v3 and v4 v v1 drive 1 voltage 16 steps of 0.5 v 11.25 - 18.75 v v v2 drive 2 voltage 128 steps of 30 mv - 6 -- 2.5 v v v3 drive 3 voltage tbf - 8 tbf v v v4 drive 4 voltage 128 steps of 30 mv - 17 -- 13.5 v r v1 drive 1 resistance - tbf 1000 w r v2 drive 2 resistance - tbf 1000 w r v3 drive 3 resistance - tbf 1000 w r v4 drive 4 resistance - tbf 1000 w c o(l) output load capacitance - 150 300 pf generated voltages status; pin vok v oh high-level output voltage 0.8v dd(host) - v dd(host) v v ol low-level output voltage v ss - 0.2v dd(host) v i o output current -- 100 m a dc/dc converter switch control outputs; pins swctrl0 and swctrl1 v oh high-level output voltage tbf - tbf v v ol low-level output voltage tbf - tbf v i o output current -- tbf m a
2003 feb 25 12 philips semiconductors objective speci?cation 240 + 1 outputs tft lcd gate driver pcf8890 12 ac characteristics v bat = 3.6 v; v ss =0v; v dd(host) = 1.8 v; vgon = 19 v; vgoff = - 8 v; t amb = - 40 to +85 c; see fig.5. all input pins v ih high-level input voltage 0.8v dd(host) - v dd(host) v v il low-level input voltage v ss - 0.2v dd(host) v i li input leakage current - 5 - +5 m a symbol parameter conditions min. typ. max. unit shift register clocks; pins rowclk0 and rowclk1 t cy(rowclk0) row clock0 cycle time tbf 64 -m s t rowclk0(h) row clock0 high time tbf 3 -m s t rowclk0(l) row clock0 low time tbf 61 -m s t cy(rowclk1) row clock1 cycle time tbf 64 -m s t rowclk1[h] row clock1 high time tbf 55 -m s t rowclk1[l] row clock1 low time tbf 9 -m s shift register for gate signals; pin framestart t su data set-up time tbf -- ns t h data hold time tbf -- ns row outputs; pins r1 to r241 t d rowclk delay c l = 300 pf --- ns symbol parameter conditions min. typ. max. unit handbook, full pagewidth mdb115 rowclk0 framestart r(x) t d t rowclk0(l) t rowclk0(h) t cy(rowclko) t h t su fig.5 timing waveforms.
2003 feb 25 13 philips semiconductors objective speci?cation 240 + 1 outputs tft lcd gate driver pcf8890 13 application information handbook, full pagewidth mdb110 pcf8890 v4 v3 v2 n.c. n.c. n.c. v1 vh swctrl0 v bat v dda to pcf8880 swctrl1 v ss c6 dc/dc converter d3 d1 d0 d4 c7 t1 t0 l1 c4 c5 c1 v ee fig.6 proposal for components. c1 = 50 nf. c4 = 33 nf. c5 and c6 = 330 nf. c7 = 3.3 m f. d0 to d3 = normal diode; breakthrough voltage >20 v. d4 = schottky diode; breakthrough voltage >6 v. t0 = bss84 (pmos vt < 2 v; r on <10 w ; v ds >50v). t1 = bsh103 (nmos vt > - 1 v; r on <5 w ; v ds >30v). l1 = 150 m h; r < 5 w ; rated current >180 ma (i.e. coil craft lpo1704-15).
2003 feb 25 14 philips semiconductors objective speci?cation 240 + 1 outputs tft lcd gate driver pcf8890 14 open short diagrams handbook, halfpage mdb117 r1 to r241 v1 v3 fig.7 row driver outputs. d book, halfpage mdb118 swctrl0, swctrl1 v bat v ss fig.8 switching control outputs. handbook, halfpage mdb119 vok v dd(host) v ss fig.9 voltage status output. handbook, halfpage mdb120 input v dd(host) v ss fig.10 inputs.
2003 feb 25 15 philips semiconductors objective speci?cation 240 + 1 outputs tft lcd gate driver pcf8890 this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... 15 bonding pad information u ll pagewidth r1 r241 r(x) dummy dummy mdb121 pcf8890 x y 0, 0 dummy view is pad side up. v ee v ee v4 v3 v ss v ss v2 v1 vh v ss v bat dummy swctrl0 v ss swctrl1 dummy v ss v dd(host) vok sysrst_n vbg vbgref iref vctrl0 vctrl1 framestart rowclk0 rowclk1 rowinv v dda(comp) dcdcclk tp6 to tp0 v ss dummy v ee v ss v ss v bat v bat . . . . . . fig.11 bonding pad location.
2003 feb 25 16 philips semiconductors objective speci?cation 240 + 1 outputs tft lcd gate driver pcf8890 table 2 bonding pad locations; all x and y coordinates are referenced to the centre of the chip (dimensions in m m; see fig.11) symbol pad coordinates bump type xy dummy 1 - 8002 +1153 1 r1 2 - 7746 +1153 2 r2 3 - 7682 +1153 2 r3 4 - 7618 +1153 2 r4 5 - 7554 +1153 2 r5 6 - 7490 +1153 2 r6 7 - 7426 +1153 2 r7 8 - 7362 +1153 2 r8 9 - 7298 +1153 2 r9 10 - 7234 +1153 2 r10 11 - 7170 +1153 2 r11 12 - 7106 +1153 2 r12 13 - 7042 +1153 2 r13 14 - 6978 +1153 2 r14 15 - 6914 +1153 2 r15 16 - 6850 +1153 2 r16 17 - 6786 +1153 2 r17 18 - 6722 +1153 2 r18 19 - 6658 +1153 2 r19 20 - 6594 +1153 2 r20 21 - 6530 +1153 2 r21 22 - 6466 +1153 2 r22 23 - 6402 +1153 2 r23 24 - 6338 +1153 2 r24 25 - 6274 +1153 2 r25 26 - 6210 +1153 2 r26 27 - 6146 +1153 2 r27 28 - 6082 +1153 2 r28 29 - 6018 +1153 2 r29 30 - 5954 +1153 2 r30 31 - 5890 +1153 2 r31 32 - 5826 +1153 2 r32 33 - 5762 +1153 2 r33 34 - 5698 +1153 2 r34 35 - 5634 +1153 2 r35 36 - 5570 +1153 2 r36 37 - 5506 +1153 2 r37 38 - 5442 +1153 2 r38 39 - 5378 +1153 2 r39 40 - 5314 +1153 2 r40 41 - 5250 +1153 2 r41 42 - 5186 +1153 2 r42 43 - 5122 +1153 2 r43 44 - 5058 +1153 2 r44 45 - 4994 +1153 2 r45 46 - 4930 +1153 2 r46 47 - 4866 +1153 2 r47 48 - 4802 +1153 2 r48 49 - 4738 +1153 2 r49 50 - 4674 +1153 2 r50 51 - 4610 +1153 2 r51 52 - 4546 +1153 2 r52 53 - 4482 +1153 2 r53 54 - 4418 +1153 2 r54 55 - 4354 +1153 2 r55 56 - 4290 +1153 2 r56 57 - 4226 +1153 2 r57 58 - 4162 +1153 2 r58 59 - 4098 +1153 2 r59 60 - 4034 +1153 2 r60 61 - 3970 +1153 2 r61 62 - 3906 +1153 2 r62 63 - 3842 +1153 2 r63 64 - 3778 +1153 2 r64 65 - 3714 +1153 2 r65 66 - 3586 +1153 2 r66 67 - 3522 +1153 2 r67 68 - 3458 +1153 2 r68 69 - 3394 +1153 2 r69 70 - 3330 +1153 2 r70 71 - 3266 +1153 2 r71 72 - 3202 +1153 2 r72 73 - 3138 +1153 2 r73 74 - 3074 +1153 2 r74 75 - 3010 +1153 2 r75 76 - 2946 +1153 2 symbol pad coordinates bump type xy
2003 feb 25 17 philips semiconductors objective speci?cation 240 + 1 outputs tft lcd gate driver pcf8890 r76 77 - 2882 +1153 2 r77 78 - 2818 +1153 2 r78 79 - 2754 +1153 2 r79 80 - 2690 +1153 2 r80 81 - 2626 +1153 2 r81 82 - 2562 +1153 2 r82 83 - 2498 +1153 2 r83 84 - 2434 +1153 2 r84 85 - 2370 +1153 2 r85 86 - 2306 +1153 2 r86 87 - 2242 +1153 2 r87 88 - 2178 +1153 2 r88 89 - 2114 +1153 2 r89 90 - 2050 +1153 2 r90 91 - 1986 +1153 2 r91 92 - 1922 +1153 2 r92 93 - 1858 +1153 2 r93 94 - 1794 +1153 2 r94 95 - 1730 +1153 2 r95 96 - 1666 +1153 2 r96 97 - 1602 +1153 2 r97 98 - 1538 +1153 2 r98 99 - 1474 +1153 2 r99 100 - 1410 +1153 2 r100 101 - 1346 +1153 2 r101 102 - 1282 +1153 2 r102 103 - 1218 +1153 2 r103 104 - 1154 +1153 2 r104 105 - 1090 +1153 2 r105 106 - 1026 +1153 2 r106 107 - 962 +1153 2 r107 108 - 898 +1153 2 r108 109 - 834 +1153 2 r109 110 - 770 +1153 2 r110 111 - 706 +1153 2 r111 112 - 642 +1153 2 r112 113 - 578 +1153 2 r113 114 - 514 +1153 2 r114 115 - 450 +1153 2 symbol pad coordinates bump type xy r115 116 - 386 +1153 2 r116 117 - 322 +1153 2 r117 118 - 258 +1153 2 r118 119 - 194 +1153 2 r119 120 - 130 +1153 2 r120 121 - 66 +1153 2 r121 122 - 2 +1153 2 r122 123 +62 +1153 2 r123 124 +126 +1153 2 r124 125 +190 +1153 2 r125 126 +254 +1153 2 r126 127 +318 +1153 2 r127 128 +382 +1153 2 r128 129 +446 +1153 2 r129 130 +574 +1153 2 r130 131 +638 +1153 2 r131 132 +702 +1153 2 r132 133 +766 +1153 2 r133 134 +830 +1153 2 r134 135 +894 +1153 2 r135 136 +958 +1153 2 r136 137 +1022 +1153 2 r137 138 +1086 +1153 2 r138 139 +1150 +1153 2 r139 140 +1214 +1153 2 r140 141 +1278 +1153 2 r141 142 +1342 +1153 2 r142 143 +1406 +1153 2 r143 144 +1470 +1153 2 r144 145 +1534 +1153 2 r145 146 +1598 +1153 2 r146 147 +1662 +1153 2 r147 148 +1726 +1153 2 r148 149 +1790 +1153 2 r149 150 +1854 +1153 2 r150 151 +1918 +1153 2 r151 152 +1982 +1153 2 r152 153 +2046 +1153 2 r153 154 +2110 +1153 2 symbol pad coordinates bump type xy
2003 feb 25 18 philips semiconductors objective speci?cation 240 + 1 outputs tft lcd gate driver pcf8890 r154 155 +2174 +1153 2 r155 156 +2338 +1153 2 r156 157 +2302 +1153 2 r157 158 +2366 +1153 2 r158 159 +2430 +1153 2 r159 160 +2494 +1153 2 r160 161 +2558 +1153 2 r161 162 +2622 +1153 2 r162 163 +2686 +1153 2 r163 164 +2750 +1153 2 r164 165 +2814 +1153 2 r165 166 +2878 +1153 2 r166 167 +2942 +1 153 2 r167 168 +3006 +1153 2 r168 169 +3070 +1153 2 r169 170 +3134 +1153 2 r170 171 +3198 +1153 2 r171 172 +3262 +1153 2 r172 173 +3326 +1153 2 r173 174 +3390 +1153 2 r174 175 +3454 +1153 2 r175 176 +3518 +1153 2 r176 177 +3582 +1153 2 r177 178 +3646 +1153 2 r178 179 +3710 +1153 2 r179 180 +3774 +1153 2 r180 181 +3838 +1153 2 r181 182 +3902 +1153 2 r182 183 +3966 +1153 2 r183 184 +4030 +1153 2 r184 185 +4094 +1153 2 r185 186 +4158 +1153 2 r186 187 +4222 +1153 2 r187 188 +4286 +1153 2 r188 189 +4350 +1153 2 r189 190 +4414 +1153 2 r190 191 +4478 +1153 2 r191 192 +4542 +1153 2 r192 193 +4606 +1153 2 symbol pad coordinates bump type xy r193 194 +4734 +1153 2 r194 195 +4798 +1153 2 r195 196 +4862 +1153 2 r196 197 +4926 +1153 2 r197 198 +4990 +1153 2 r198 199 +5054 +1153 2 r199 200 +5118 +1153 2 r200 201 +5182 +1153 2 r201 202+ +5246 +1153 2 r202 203 +5310 +1153 2 r203 204 +5374 +1153 2 r204 205 +5438 +1153 2 r205 206 +5502 +1153 2 r206 207 +5566 +1153 2 r207 208 +5630 +1153 2 r208 209 +5694 +1153 2 r209 210 +5758 +1153 2 r210 211 +5822 +1153 2 r211 212 +5886 +1153 2 r212 213 +5950 +1153 2 r213 214 +6014 +1153 2 r214 215 +6078 +1153 2 r215 216 +6142 +1153 2 r216 217 +6206 +1153 2 r217 218 +6270 +1153 2 r218 219 +6334 +1153 2 r219 220 +6398 +1153 2 r220 221 +6462 +1153 2 r221 222 +6526 +1153 2 r222 223 +6590 +1153 2 r223 224 +6654 +1153 2 r224 225 +6718 +1153 2 r225 226 +6782 +1153 2 r226 227 +6846 +1153 2 r227 228 +6910 +1153 2 r228 229 +6974 +1153 2 r229 230 +7038 +1153 2 r230 231 +7102 +1153 2 r231 232 +7166 +1153 2 symbol pad coordinates bump type xy
2003 feb 25 19 philips semiconductors objective speci?cation 240 + 1 outputs tft lcd gate driver pcf8890 r232 233 +7230 +1153 2 r233 234 +7294 +1153 2 r234 235 +7358 +1153 2 r235 236 +7422 +1153 2 r236 237 +7486 +1153 2 r237 238 +7550 +1153 2 r238 239 +7614 +1153 2 r239 240 +7678 +1153 2 r240 241 +7742 +1153 2 r241 242 +7806 +1153 2 dummy 243 +7998 +1153 2 v bat 244 +7773 - 1232 3 v ss 245 +7663 - 1232 4 v ee 246 +7553 - 1232 5 dummy 247 +7443 - 1232 6 dummy 248 +7223 - 1232 7 dummy 249 +7113 - 1232 7 dummy 250 +7003 - 1232 7 dummy 251 +6893 - 1232 7 dummy 252 +6783 - 1232 7 dummy 253 +6673 - 1232 7 dummy 254 +6563 - 1232 7 dummy 255 +6453 - 1232 7 dummy 256 +6343 - 1232 7 dummy 257 +6233 - 1232 7 dummy 258 +6123 - 1232 7 dummy 259 +6013 - 1232 7 dummy 260 +5903 - 1232 7 dummy 261 +5793 - 1232 7 dummy 262 +5683 - 1232 7 dummy 263 +5573 - 1232 7 dummy 264 +5463 - 1232 7 dummy 265 +5353 - 1232 7 dummy 266 +5243 - 1232 7 dummy 267 +5133 - 1232 7 dummy 268 +5023 - 1232 7 dummy 269 +4913 - 1232 7 dummy 270 +4803 - 1232 7 dummy 271 +4693 - 1232 7 symbol pad coordinates bump type xy dummy 272 +4583 - 1232 7 dummy 273 +4473 - 1232 7 dummy 274 +4363 - 1232 7 dummy 275 +4253 - 1232 7 dummy 276 +4143 - 1232 7 dummy 277 +4033 - 1232 7 dummy 278 +3923 - 1232 7 dummy 279 +3813 - 1232 7 dummy 280 +3703 - 1232 7 dummy 281 +3593 - 1232 7 dummy 282 +3483 - 1232 7 dummy 283 +3373 - 1232 7 dummy 284 +3263 - 1232 7 dummy 285 +3153 - 1232 7 dummy 286 +3043 - 1232 7 dummy 287 +2933 - 1232 7 dummy 288 +2823 - 1232 7 dummy 289 +2713 - 1232 7 dummy 290 +2603 - 1232 7 dummy 291 +2493 - 1232 7 dummy 292 +2383 - 1232 7 dummy 293 +2273 - 1232 7 dummy 294 +2163 - 1232 7 dummy 295 +2053 - 1232 7 dummy 296 +1943 - 1232 7 dummy 297 +1833 - 1232 7 dummy 298 +1723 - 1232 7 dummy 299 +1613 - 1232 7 dummy 300 +1503 - 1232 7 dummy 301 +1393 - 1232 7 dummy 302 +1283 - 1232 7 dummy 303 +1173 - 1232 7 dummy 304 +1063 - 1232 7 dummy 305 +953 - 1232 7 dummy 306 +843 - 1232 7 dummy 307 +733 - 1232 7 dummy 308 +623 - 1232 7 dummy 309 +513 - 1232 7 dummy 310 +403 - 1232 7 symbol pad coordinates bump type xy
2003 feb 25 20 philips semiconductors objective speci?cation 240 + 1 outputs tft lcd gate driver pcf8890 dummy 311 +293 - 1232 7 dummy 312 +183 - 1232 7 dummy 313 +73 - 1232 7 dummy 314 - 37 - 1232 7 dummy 315 - 147 - 1232 7 dummy 316 - 257 - 1232 7 dummy 317 - 367 - 1232 7 dummy 318 - 477 - 1232 7 dummy 319 - 587 - 1232 7 dummy 320 - 697 - 1232 7 dummy 321 - 807 - 1232 7 dummy 322 - 917 - 1232 7 dummy 323 - 1027 - 1232 7 dummy 324 - 1137 - 1232 7 dummy 325 - 1247 - 1232 7 v ss 326 - 1357 - 1232 8 v ee 327 - 1467 - 1232 9 v ee 328 - 1577 - 1232 9 v ee 329 - 1687 - 1232 9 v4 330 - 1797 - 1232 10 v4 331 - 1907 - 1232 10 v3 332 - 2017 - 1232 11 v3 333 - 2127 - 1232 11 v ss 334 - 2237 - 1232 8 v2 335 - 2347 - 1232 12 v2 336 - 2457 - 1232 12 v1 337 - 2567 - 1232 13 v1 338 - 2677 - 1232 13 vh 339 - 2787 - 1232 14 vh 340 - 2897 - 1232 14 v ss 341 - 3007 - 1232 15 v bat 342 - 3117 - 1232 10 v bat 343 - 3227 - 1232 10 v bat 344 - 3337 - 1232 10 dummy 345 - 3447 - 1232 10 dummy 346 - 3557 - 1232 10 swctrl0 347 - 3667 - 1232 6 v ss 348 - 3777 - 1232 16 swctrl1 349 - 3887 - 1232 6 symbol pad coordinates bump type xy dummy 350 - 3997 - 1232 10 dummy 351 - 4107 - 1232 10 v ss 352 - 4217 - 1232 15 v ss 353 - 4327 - 1232 15 v ss 354 - 4437 - 1232 15 v ss 355 - 4547 - 1232 15 v dd(host) 356 - 4657 - 1232 17 v dd(host) 357 - 4667 - 1232 17 v dd(host) 358 - 4877 - 1232 17 vok 359 - 4987 - 1232 6 sysrst_n 360 - 5097 - 1232 6 vbg 361 - 5207 - 1232 6 vbgref 362 - 5317 - 1232 6 iref 363 - 5427 - 1232 6 vctrl0 364 - 5537 - 1232 6 vctrl1 365 - 5647 - 1232 6 framestart 366 - 5757 - 1232 6 rowclk0 367 - 5867 - 1232 6 rowclk1 368 - 5977 - 1232 6 rowinv 369 - 6087 - 1232 6 v dda(comp) 370 - 6197 - 1232 6 dcdcclk 371 - 6307 - 1232 6 tp6 372 - 6417 - 1232 6 tp4 373 - 6527 - 1232 6 tp5 374 - 6637 - 1232 6 tp0 375 - 6747 - 1232 6 tp1 376 - 6857 - 1232 6 tp2 377 - 6967 - 1232 6 tp3 378 - 7077 - 1232 6 v ss 379 - 7187 - 1232 18 dummy 380 - 7297 - 1232 6 dummy 381 - 7407 - 1232 6 v ee 382 - 7517 - 1232 19 v ss 383 - 7627 - 1232 20 v bat 384 - 7737 - 1232 21 symbol pad coordinates bump type xy
2003 feb 25 21 philips semiconductors objective speci?cation 240 + 1 outputs tft lcd gate driver pcf8890 table 3 bonding pad information table 4 bump dimensions item dimensions pad pitch 64 m m bump dimension see fig.12 chip size 16300 2950 m m wafer thickness (bumps not included) 380 m m mdb116 bump type 1 40 m m 4 m m 4 m m 4 m m 4 m m 4 m m 100 m m 59 m m bump type 2 40 m m 4 m m 100 m m 59 m m bump types 3-22 40 m m h 1) v3 v4 fig.12 bump dimensions. (1) see table 4 bump type h ( m m) 3 333 4 234 5 273 6 106 7 180 8 344 9 113 10 212 11 245 12 278 13 179 14 311 15 410 16 442 17 166 18 512 19 272 20 233 21 383 16 tray information handbook, halfpage mdb122 pcf8890v1 fig.13 chip orientation.
2003 feb 25 22 philips semiconductors objective speci?cation 240 + 1 outputs tft lcd gate driver pcf8890 17 data sheet status notes 1. please consult the most recently issued data sheet before initiating or completing a design. 2. the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the latest information is available on the internet at url http://www.semiconductors.philips.com. 3. for data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. level data sheet status (1) product status (2)(3) definition i objective data development this data sheet contains data from the objective speci?cation for product development. philips semiconductors reserves the right to change the speci?cation in any manner without notice. ii preliminary data quali?cation this data sheet contains data from the preliminary speci?cation. supplementary data will be published at a later date. philips semiconductors reserves the right to change the speci?cation without notice, in order to improve the design and supply the best possible product. iii product data production this data sheet contains data from the product speci?cation. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. relevant changes will be communicated via a customer product/process change noti?cation (cpcn). 18 definitions short-form specification ? the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values definition ? limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the specification is not implied. exposure to limiting values for extended periods may affect device reliability. application information ? applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 19 disclaimers life support applications ? these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes ? philips semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. when the product is in full production (status production), relevant changes will be communicated via a customer product/process change notification (cpcn). philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
2003 feb 25 23 philips semiconductors objective speci?cation 240 + 1 outputs tft lcd gate driver pcf8890 bare die ? all die are tested and are guaranteed to comply with all data sheet limits up to the point of wafer sawing for a period of ninety (90) days from the date of philips' delivery. if there are data sheet limits not guaranteed, these will be separately indicated in the data sheet. there are no post packing tests performed on individual die or wafer. philips semiconductors has no control of third party procedures in the sawing, handling, packing or assembly of the die. accordingly, philips semiconductors assumes no liability for device functionality or performance of the die or systems after third party sawing, handling, packing or assembly of the die. it is the responsibility of the customer to test and qualify their application in which the die is used.
? koninklijke philips electronics n.v. 2003 sca75 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. philips semiconductors C a worldwide company contact information for additional information please visit http://www.semiconductors.philips.com . fax: +31 40 27 24825 for sales of?ces addresses send e-mail to: sales.addresses@www.semiconductors.philips.com . printed in the netherlands 403512/01/pp 24 date of release: 2003 feb 25 document order number: 9397 750 10898

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